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NCP5008, NCP5009 Backlight LED Boost Driver
The NCP5008/NCP5009 is a high efficiency boost converter operating in current loop control mode to drive Light Emitting Diode. The current mode regulation allows a uniform brightness of the LEDs.
Features http://onsemi.com MARKING DIAGRAM
* * * * * * * * * * * * *
2.7 to 6.0 V Input Voltage Range Output Voltage from Vbat to 15 V 3.0 mA Quiescent Supply Current Automatically LEDs Current Matching No External Sense Resistor Includes Dimming Function Programmable or Automatic Current Output Mode LOCAL or REMOTE Control Facility Photo Transistor Sense Feedback Input Inductor Based Converter brings High Efficiency Low Noise DC/DC Converter All Pins are Fully ESD Protected Pb-Free Package is Available
1
Micro 10 DM SUFFIX CASE 846B 1
5Tx AYW G G
5Tx = Device Number x = 8 or 9 A = Assembly Location Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
Typical Applications
PIN CONNECTIONS
Iref NC Vbat C1 U1 CS VBIAS CLOCK GND 1 2 3 4 5 NCP5008 10 9 8 7 6 Vbat L1 L2 Iout GND LOCAL
* LED Display Back Light Control * High Efficiency Step Up Converter
R1 30 k GND
1 2
Iref PHOTO
Vbat L1
10 9
10 mF/6.3 V
Iref Photo Q1 NPN-PHOTO GND Vcc 4 VBIAS 3 CS 5 CLK D1 LED NCP5009 D2 LED C2 2.2 mF/16 V 8 7 GND 6 LOCAL L2 D3 LED D4 LED D5 MBR0520 Vbat L1 22 mH CS VBIAS CLOCK
1 2 3 4 5 NCP5009
10 9 8 7 6
Vbat L1 L2 Iout GND LOCAL
MICROCONTROLLER
GND
ORDERING INFORMATION
Device NCP5008DMR2 Package Micro 10 Shipping 4000 / Tape & Reel
GND
NCP5008DMR2G NCP5009DMR2
Micro 10 4000 / Tape & Reel (Pb-Free) Micro 10 4000 / Tape & Reel
GND
Figure 1. Typical Battery Powered LED Boost Driver
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NCP5008/D
(c) Semiconductor Components Industries, LLC, 2006
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April, 2006 - Rev. 7
NCP5008, NCP5009
BACK LIGHT WHITE LED CURRENT DRIVE CONTROLLER
Vbat BandGap Vbat POR POR 1R8 R1 10 Vbat
Serial To Parallel Latches
VBIAS CLK CS
4 5 3 50 k
Iout Reference 1:8 Vref Selection
Isense 9 L1
Vbat
+
A=10 GND
-
Vbat Vbat Vref Q2 POR 50 k Vbat Iout Q1 LOCAL Iref PHOTO (See Note) 6 1 2 GND Vbat Vbat + - Vbat_OK BANDGAP REFERENCE
8
L2
CONTROLLER
7 GND
BandGap
GND
NOTE: This functionality is NOT implemented on the NCP5008 type.
Figure 2. Block Diagram
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NCP5008, NCP5009
PIN FUNCTION DESCRIPTION
Pin 1 Symbol Iref Type INPUT Description This pin provides the output current range adjustment by means of a resistor connected to ground. The current output tolerance depends upon the accuracy of this resistor. Using a "1% metal film resistor, or better, yields the best output current accuracy. This pin provides an access to the output current control loop for the NCP5009 version. The current sunk to ground from this pin is subtracted from the output current mirror. Primary use is the ambient light automatic adjustment by means of an external photo transistor connected across this pin and ground. The output current decreases as the ambient light increases. The internal circuit provides a 1/1 current ratio with the Iref defined by the resistor connected from pin 1 to ground. This current shall be limited to 65 mA. This functionality is NOT implemented on the NCP5008 type. Negative going Chip Select logic input. This pin is used to select the NCP5008/ NCP5009 and validate the clock/data when CS = Low. The internal shift register is automatically clear to zero upon the falling edge, thanks to a 20 ns built-in one shoot. The built-in pull-up resistor disables the device when the CS pin is left open. This pin should be connected to Vbat. The clock signal connected to this pin is used to serially shift right the internal preset high logic level. The clock is valid between the falling edge and until the rising edge of the CS. There is neither a feedback nor an overflow control. If the clock count exceeds 8 bits, the internal register is clear, the output current is forced to zero and the device comes back to the shutdown mode. This pin is used to select the mode of operation. * When LOCAL = High or Open, the chip is controlled by two digital lines:CS and CLOCK. The output current is programmed by the logic control of these pins, allowing a current adjustment within the range defined by the Iref resistor. * When LOCAL = Low, the chip is turned ON /OFF by means of the CS line, the CLOCK pins being deactivated. The output current is constant, as defined by the Iref resistor value. In order to minimize the standby current a dynamic pull-up resistor is activated when POR is High, this pull-up resistor being disconnected when LOCAL = Low. This pin is the system ground for the NCP5008/NCP5009 and carries both the Power and the Digital signals. High quality ground must be provided to avoid spikes and/or uncontrolled operation. Care must be observed to avoid high-density current flow in a limited PCB copper track. This pin is the power side of the external inductor and must be connected either to the external Schottky diode (see Figure 22) or directly to one external LED (see Figure 23). It provides the output current to the load. Since the boost converter operates in a current loop mode, the output voltage can range up to +15 V but shall not extend this limit. The user must make sure this voltage will not be exceeded during the normal operation of this part. An external low cost ceramic capacitor (2.2 mF/16 V, ESR < 100 mW) is recommended to smooth the current flowing into the diode(s), thus limiting the noise created by the fast transients present in this circuitry. Care must be observed to avoid EMI though the PCB copper tracks connected to this pin. The return side of the external inductor shall be connected to this pin. Typical application will use a 22 mH, size 1210, to handle the 2.8 to 364 mA max range. On the other hand, when the desired output current is above 20 mA, the inductor shall have an ESR < 1.0 W. The output current tolerance can be improved by using a larger inductor value. The external voltage supply is connected to this pin. A high quality reservoir capacitor must be connected across pin 10 and Ground to achieve the specified output voltage parameters. A 10 mF/6.3 V, low ESR capacitor must be connected as close as possible across pin 10 and ground pin 7. The X5R ceramic types are recommended.
2
PHOTO
SIGNAL
3
CS
INPUT
4 5
VBIAS CLOCK
POWER INPUT
6
LOCAL
INPUT
7
GND
POWER
8
L2
POWER
9
L1
POWER
10
Vbat
POWER
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NCP5008, NCP5009
Table 1. Shift Register Bits Assignment and Functions
SetReg shift register (Note: The register content is latched upon CS positive going).
B7 Bn Value After POR Iout Peak (mA) 0 Iref*k*7.5 B6 0 Iref*k*6.5 B5 0 Iref*k*5.5 B4 0 Iref*k*4.5 B3 0 Iref*k*3.5 B2 0 Iref*k*2.5 B1 0 Iref*k*1.5
LOCAL L L H or Open H or Open H or Open
CLOCK X X X
CS H L H L L
B1-B7 X X No Change No Change Qdata Bn
Output Current 0 Iref * k Iref * k * (Bn + 0.5) Iref * k * (Bn + 0.5) Iref * k * (Bn + 0.5)
The register is clear to 0 during the first 20 ns following the CS falling edge. Note: Coefficient Value (internal ratio): k = 746 Maximum output peak current @ B7 = 1 and Iphoto = 0 mA : Iout peak = Iref * (7 + 0.5) * 746 = Iref * 5595
V Iref + ref + 1.24 V R1 R1
MAXIMUM RATINGS
Rating Power Supply Output Power Supply Voltage Compliance Digital Input Voltage Digital Input Current Human Body Model: R = 1500 W, C = 100 pF Machine Model Micro 10 Package Power Dissipation @ TA = +85C Thermal Resistance, Junction-to-Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Symbol Vbat, VBIAS VL2 CLK, CS ESD ESD PD RThja TA TJ TJmax Tstg Value 7.0 16 -0.3 tV tVbat + 3.0 V 1.0 "2.0 "200 200 200 -25 to +85 -25 to +125 +150 -65 to +150 Unit V V V mA kV V mW C/W C C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NCP5008, NCP5009
POWER SUPPLY SECTION (-25C to +85C ambient temperature, unless otherwise noted.)
Rating Power Supply Power Supply Threshold Startup Voltage Output Load Voltage Compliance Pulsed Current Regulation Range Continuous DC Current in the Load Output Pulsed Current Tolerance @ Vbat = 3.6 V, L1 = 22 mH/0.71 W, Rref "1%, ILED = 20 mA (Note 1) Output Leakage @ LOCAL = 0, CS = H, Vout = 15 V, Vbat = 6.0 V Standby Current @ Iout = 0 mA, CS = H, CLK = H, Vbat = VBIAS = 3.6 V Standby Current @ Iout = 0 mA, CS = H, CLK = H, Vbat = VBIAS = 6.0 V Operating Current @ Vbat = VBIAS = 3.6 V, Iref = 30 mA, CLK = H, CS = L, LOCAL = Open Boost Internal Oscillator Clock @ L1 = 22 mH, Vbat = VBIAS = 3.6 V, Iout = 20 mA (Vout = 14 V) 1. The tolerance refers to the 20 mA to 70 mA current range. Pin 10 10 8 8 8 8 8 10 10 10 - Symbol Vbat VbatThr Vout Iout Iout Iout Iout Istdb Istdb Iope Fosc Min 2.7 - - 0 - - - - - - - Typ - 2.3 - - - "5.0 - 3.0 - 600 300 Max 6.0 2.7 15.0 400 75 - 500 - 10 - mA - kHz Unit V V V mA mA % nA mA mA
DIGITAL SECTION (-25C to +85C ambient temperature, unless otherwise noted.)
Rating High Level Input Voltage Low Level Input Voltage Input Capacitance High Level Input Voltage Low Level Input Voltage Input Capacitance LOCAL Pullup Resistor LOCAL Leakage Current CS Pullup Resistor Minimum CS Low Time Clock Frequency CLOCK tr and tf Internal Register Clear Internal Power on Reset Width 2. Digital inputs undershoot < - 0.30 V, Digital inputs overshoot < 0.30 V. (Note 2) (Note 2) (Note 2) (Note 2) Pin 3, 5 Symbol VIH VIL Cin VIH VIL Cin Rloc ILoc Rcs Tcssetup FCLK trCLK, tfCLK tclear tPOR Min 0.7*Vbat - - - - - 20 - 20 250 - 10 10 - Typ - - 10 0.6*Vbat 0.4*Vbat 10 - - - - - - 30 100 Max Vbat 0.3*Vbat - - - - 80 100 80 - 5.0 - - - Unit V V pF V V pF kW nA kW ns MHz ns ns ms
6
6 9 3 3 5 5 - -
ANALOG SECTION (-25C to +85C ambient temperature, unless otherwise noted.)
Rating Output Voltage Range Reference @ 2.5 mA < Iref < 65 mA (Note 3) Maximum Output Current Range Ratio Minimum Output Current Range Ratio Output Current Sense Resistor Output Voltage Range Reference @ 2.5 mA < Ipho < 65 mA Output Current Stabilization tdelay following a DC/DC startup Internal NMOS Resistor @ Vbat = 3.6 V Internal Comparator Delay Time Pin 1 8 8 10, 9 2 8 8 - Symbol Vref Iout Iout Rs Vpho Ioutdly QRDSON Tdcomp Min 1.20 - - - 1.20 - - - Typ 1.24 5595 1119 1.8 1.24 100 2.2 60 Max 1.28 - - 5.0 1.28 - 3.0 - Unit V - - W V ms W ns
3. The overall tolerance depends upon the accuracy of the external resistor. Using a 1%/low PPM metal film resistor is recommended to achieve "5% output current tolerance.
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NCP5008, NCP5009
TYPICAL OPERATING CHARACTERISTICS
Condition: Typical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW
80 75 EFFICIENCY (%) 70 65 60 55 50 0 5 10 15 20 25 30 35 ILED (mA) Vbat = 3.6 V 80 75 EFFICIENCY (%) 70 65 60 55 Vbat = 3.0 V 50 0 5 10 15 20 25 30 35 ILED (mA) Vbat = 4.2 V Vbat = 3.6 V
Vbat = 4.2 V
Vbat = 3.0 V
Figure 3. Efficiency vs. Load Current @ 4 LEDS (Vload = 4*Vf 14.2 V)
85 Vbat = 4.2 V 80 EFFICIENCY (%) Vbat = 3.6 V EFFICIENCY (%) 90 100
Figure 4. Efficiency vs. Load Current @ 3 LEDS (Vload = 3*Vf 10.5 V)
Vout =7.5 V Iled = 40 mA
75
80 Vout = 15 V Iled = 20 mA
Vbat = 3.0 V
70
70
65
60
60 0 5 10 15 20 25 30 35 ILED (mA)
50 2.5
3.0
3.5
4.0
4.5 Vbat (V)
5.0
5.5
6.0
6.5
Figure 5. Efficiency vs. Load Current @ 2 LEDS (Vload = 2*Vf 7.1 V)
100 Vbat = 6.0 V 95 EFFICIENCY (%) 5.0 V 90 4.2 V Ipeak (mA) 300 250 200 150 100 3.6 V 3.0 V 75 0 10 20 30 40 50 60 70 ILED (mA) 0 0 50 400 350
Figure 6. Efficiency vs. Vbat @ Vout = 15 V/Iled = 20mA and Vout = 7.5 V/Iled = 40 mA
Bn 7 6 5 4 3 2 1
85
80
20
40 Iref (mA)
60
80
Figure 7. Efficiency vs. Load Current @ 4 LEDS (Vload = 2 strings of 2 LEDs in series = 7.1V) http://onsemi.com
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Figure 8. Inductor peak Current vs. Iref @ Bn = {1, 2, 3, 4, 5, 6, 7}
NCP5008, NCP5009
TYPICAL OPERATING CHARACTERISTICS
Condition: Typical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW
50 45 40 Ipeak ERROR (%) 60 70 35 ILED (mA) 30 25 20 15 10 5 0 0 10 20 30 40 50 Iref (mA) Vload = 15 V Vload = 10 V 20 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 300 350 400
THEORETICAL Ipeak (mA)
Figure 9. Load Current (Iled) vs. Iref @ Vbat = 3.6 V, Vload = 15 V and 10 V
200 180 160 140 Ipeak (mA) 120 100 80 60 40 20 0 0 10 20 Iphoto (mA) 30 40 3.5 3.0 2.4 Istby (mA) Measured 5.5 5.0 4.5 4.0 Theoretical 6.0 7.0 6.5
Figure 10. Inductor Peak Current Error vs. Theoretical Inductor Peak Current
2.8
3.2
3.6
4.0
4.4
4.8
5.2
5.6
6.0
Vbat (V)
Figure 11. Inductor Peak Current vs. Iphoto @ Iref = 34 mA
80 75 EFFICIENCY (%) 70 65 60 Vbat = 3.6 V 55 50 0 5 10 15 20 25 30 35 ILED (mA) Vbat = 3.0 V EFFICIENCY (%) Vbat = 4.2 V 85 80 75
Figure 12. Stand by Current vs. Vbat @ T = 20C
Vbat = 4.2 V Vbat = 3.6 V
70 65 60 55 Vbat = 3.0 V 50 0 5 10 15 20 25 30 35 ILED (mA)
Figure 13. Efficiency vs. Load Current @ 4 LEDS (Vload = 4*Vf 14.2 V)
Figure 14. Efficiency vs. Load Current @ 3 LEDS (Vload = 3*Vf 10.5 V)
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NCP5008, NCP5009
TYPICAL OPERATING CHARACTERISTICS
Condition: Typical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW
90 Vbat = 4.2 V 85 EFFICIENCY (%) EFFICIENCY (%) 80 75 70 65 60 0 5 10 15 20 25 30 35 ILED (mA) Vbat = 3.6 V 95 90 4.2 V 85 80 3.6 V 75 3.0 V 70 0 10 20 30 40 50 60 70 ILED (mA) 5.0 V 100 Vbat = 6.0 V
Vbat = 3.0 V
Figure 15. Efficiency vs Load Current @ 2 LEDS (Vload = 2*Vf 7.1 V)
Figure 16. Efficiency vs Load Current @ 4 LEDS (Vload = 2 strings of 2 LEDs in series = 7.1 V)
Operating Description
Output tCLKmin Vbat ON
90% 50% 10%
tf
tr
OFF Input 0.30* Vbat 0.70* Vbat Vbat
Figure 17. Digital Timing Definitions
Figure 18. Typical Schmitt Trigger Characteristic
Input Schmitt Triggers All the Logic Input pins have built-in Schmitt trigger circuits to prevent the NCP5008/NCP5009 against uncontrolled operation. The typical dynamic characteristics of the related pins are depicted in Figure 18. The output signal is guaranteed to go High when the input voltage is above 0.70*Vbat, and will go Low when the input voltage is below 0.30*Vbat. Local Mode When the system operate in a Local Mode (Pin 6, /LOCAL=Low), the output current depends solely upon
the current drawn pin 1. The clock signal is irrelevant and the output current is derived by equation Iout = Iref * k, the internal constant k being equal to 746. ESD Protection The NCP5008/NCP5009 includes silicon devices to protect the pins against the ESD spikes voltages. To cope with the different ESD voltages developed in the applications, the built-in structures have been designed to handle $2.0 kV in Human Body Model (HBM) and $200 V in Machine Model (MM) and on each pin.
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NCP5008, NCP5009
Remote Control Programming Sequence
tCSsetup
CS tclear CLEAR
CLK Qdata
B1 B2 B3 B4 B5 B6 B7 Iout ref Output Current Programmed Register Internal Latch Data and Reset
Last Latched Bit
Ioutdly
Iout
Figure 19. Programming Sequence
Upon CS transition from High to Low, the internal sequence will take place: - Qdata is internally set to high level. - Upon positive going transition of the next CLK signal, the Qdata is shifted to the next Bn stage. - Clear the Qdata flip-flop upon the positive going of the SetReg[B1] transient. The sequence keeps going until CS = High. When the CS line returns to a High state, the programming output current flip-flop is set according to the previous state of the shift register and SetReg B[1-7] is cleared afterward. Depending upon the CS width, for a given CLK period, the last SetReg bit will be latched and the output current
will be adjusted accordingly. If the number of CLK pulses is higher than 7, the Qdata is lost and the SetReg register bits B[1-7] are in the Low state, yielding a zero output current. The internal shift register can be clear by sending more than 7 pulses to the CLK pin when the pin CS is low. If the internal shift register is clear upon the CS transition from Low to High, the device will be placed or maintained in the shut down mode. When the register content is higher than zero, the DC/DC is activated and a 100 ms delay (typical) is necessary to stabilize the output current to the programmed value.
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NCP5008, NCP5009
Set Up Output Current Range
Vbat
1 Vbat
1
+ -
BandGap
Iref
Vbat
GND Iref Rref 30 k Vbat Iphoto 1 1:746
Iout Reference = (Iref-Iphoto)*746*(Bn+0.5)
GND
1 Vbat
1 I = (Iref-Iphoto)*(Bn+0.5)
1 + - BandGap GND
1
1
1:Bn
2:1
GND GND
GND
GND
GND Photo Q1 NPN-PHOTO
GND
Figure 20. Functional Diagram
The current sunk to ground on PHOTO pin is subtracted from the current sunk to ground on Iref pin. The result is multiplied by the programmed value (Bn) and then multiplied by the constant factor ratio (k = 746) in the current mirror. The constant factor k is a ratio between the current on Iout sense and the Iout reference internally fixed. The output current reference is: Ipeak = Ivalley + (Iref - Iphoto) * Bn * k.
Where k = 746, Bn represents the bit of the internal shift register, range from 1 to 7, and Ivalley = (Iref - Iphoto) * 0.5 * k. We can write also Ipeak = (Iref - Iphoto) * (Bn + 0.5) * k. Please find below the formula to quickly calculate R1 resistor (resistor on Iref pin):
Iref + 1.24 R1
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NCP5008, NCP5009
DC/DC Converter Operation The DC/DC converter operates with a boost structure depicted in Figure 21, the load being supplied by the pulsed current coming from the external inductor L1. The current is monitored by the internal sense resistor Rsense to Set and Reset the flip-flop U3 and U6 according to the comparators U2 and U4 output state.
Vbat Vbat + U1 - Vbat GND Ipeak_ref + U2 - Vbat Ivalley_ref + U4 - GND GND POR C2 2.2 mF/16 V GND U6 L1 22 mH U3 L2 D5 MBR0520 U5 U7 Q1 D4 LED D3 LED D2 LED D1 LED GND Rsense 1R8 L1
Vbat
GND
Figure 21. Basic DC/DC Boost Structure
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NCP5008, NCP5009
Output Load Drive In order to make profit of the built-in Boost capabilities, one shall operate the NCP5008/NCP5009 in the continuous output current mode. Such a mode is achieved by using and external reservoir capacitor (preferably a low ESR ceramic type) across the LED as depicted in Figures 22, 23, 24, 25, and 26. Using an extra photo sensor is not mandatory and the related pin 2 can be either left open or connected to Vbat, but must not be grounded on the NCP5009 version only. At this point, the designer must carefully analyze two parameters: 1. The output voltage must be limited to 15 V maximum. It's the designer responsibility to make sure that spike voltages beyond the maximum rating will not exist across pin 8 and ground. Depending upon a specific application (Vbat voltage, PCB layout...), using an external voltage clamp could be necessary. 2. The peak current flowing into the LED diodes shall be within the maximum ratings specified for these devices. The Schottky diode D5, associated with capacitor C2, provides a rectification and filtering function. When a pulse-operating mode is acceptable: * The LEDs brightness can be controlled in LOCAL mode with a PWM on CS pin as depicted in Figure 24. * Or the Schottky can be removed and replaced by at least one LED diode as depicted in Figure 23.
TYPICAL APPLICATION CIRCUIT
Vbat C1 U1 R1 30 k GND Vcc Q1 NPN-PHOTO L1 22 mH 1 2 Iref PHOTO Vbat L1 10 9 10 mF/6.3 V GND
Vbat GND
MICROCONTROLLER
4 VBIAS 3 CS 5 CLK NCP5009 D1 GND LED
8 7 GND 6 LOCAL L2 GND D2 LED C2 2.2 mF/16 V D3 LED D4 LED
D5
MBR0520
GND
Figure 22. Basic DC Current Mode Operation in REMOTE Control
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NCP5008, NCP5009
Vbat C1 U1 R1 30 k GND Vcc 1 2 Iref PHOTO Vbat L1 10 9 10 mF/6.3 V GND
Q1 NPN-PHOTO GND
Vbat
L1 22 mH
MICROCONTROLLER
4 VBIAS 3 CS 5 CLK NCP5009
8 7 GND 6 LOCAL L2 GND D3 D4 LED
GND LED C2 1.0 mF/16 V
GND
Figure 23. Typical Semi-Pulsed Mode of Operation in REMOTE Mode
Vbat C1 U1 R1 30 k GND 1 2 Iref PHOTO Vbat L1 10 9 10 mF/6.3 V GND
Q1 NPN-PHOTO GND
Vbat
L1 22 mH
PWM
4 VBIAS 3 CS 5 CLK NCP5009
8 7 GND 6 LOCAL L2 GND
D5
MBR0520
D1 LED
D2 LED C2
D3 LED
D4 LED
GND
2.2 mF/16 V
Figure 24. PWM Current Control Mode Operation in LOCAL Mode
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NCP5008, NCP5009
Vbat C1 U1 R1 DAC 30 k 1 2 Iref PHOTO Vbat L1 10 9 10 mF/6.3 V GND
Q1 NPN-PHOTO
Vbat GND
L1 22 mH
OFF ON
4 VBIAS 3 CS 5 CLK NCP5009
8 7 GND 6 LOCAL L2 GND
D5
MBR0520
D1 LED
D2 LED C2
D3 LED
D4 LED
GND
2.2 mF/16 V
Figure 25. DAC Current Control Mode Operation in LOCAL Mode
Vbat C1 U1 R1 30 k GND 1 2 Iref PHOTO Vbat L1 10 9 10 mF/6.3 V GND
Q1 NPN-PHOTO
Vbat GND
L1 22 mH
OFF ON
4 VBIAS 3 CS 5 CLK NCP5009
8 7 GND 6 LOCAL L2 GND
D5
MBR0520
D1 LED
D2 LED C2
D3 LED
D4 LED
GND
2.2 mF/16 V
Figure 26. Basic DC Current Mode Operation in LOCAL Mode
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NCP5008, NCP5009
TYPICAL LEDS LOAD MAPPING
75 mA Load+ D1 LED 6.7 V D2 LED D4 LED D6 LED D8 LED D10 LED D3 LED D5 LED D7 LED D9 LED
GND
Example 1
50 mA Load+ D1 LED 60 mA Load+ D1 LED 6.7 V D2 LED D4 LED D6 LED D3 LED D6 LED D9 LED D3 LED D5 LED 10.4 V D2 LED D5 LED D8 LED D4 LED D7 LED
GND
Example 2
GND
Example 3
Figure 27. Three different examples of load can be driven by the NCP5009 or NCP5008 Condition: Vbat = 3.6 V, L = 22 mH
MANUFACTURER REFERENCE
Design Ref D5 L1 C1 C2 Q1 D1 to D4 Value/Reference or Size MBR0520/SOD-123 22 mH/1210 10 mF/ 6.3 V/0805 2.2 mF/16 V/1206 SFH320/PLCC2 White LED Manufacturer ON Semiconductor MURATA MURATA MURATA Osram Osram Reference Number MBR0520 LQH3C220K34 GRM40 X5R 106K 6.3 GRM42-6 X7R 225K 16 SFH320 LW5413-VBW-1
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NCP5008, NCP5009
LAYOUT EXAMPLE
Figure 28. Typical Printed Circuit Layout (the Top Silk Screen and the Top Layer)
The Figure 28 represents the typical printed circuit layout based on the basic application Figure 1. This application has been routed on a single copper layer to save cost. A dual side PCB has better noise protection and can be the right choice for an industrial system. In order to avoid voltage spikes, care must be observed to group the capacitors, the inductor, the Schottky diode and the
integrated circuit in the same area. On the other hand, using large copper tracks to reduce the resistor connectivity is strongly recommended. Obviously, the connectors GND, CLK, CS, Vbat and Load are for engineering purpose only and not for final application.
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NCP5008, NCP5009
PACKAGE DIMENSIONS
Micro10 CASE 846B-03 ISSUE D
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION "A" DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION "B" DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846B-01 OBSOLETE. NEW STANDARD 846B-02 DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.95 1.10 0.20 0.30 0.50 BSC 0.05 0.15 0.10 0.21 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.037 0.043 0.008 0.012 0.020 BSC 0.002 0.006 0.004 0.008 0.187 0.199 0.016 0.028
-A-
K
-B-
PIN 1 ID
G
D 8 PL 0.08 (0.003)
M
TB
S
A
S
0.038 (0.0015) -T-
SEATING PLANE
C H J L
SOLDERING FOOTPRINT*
10X
1.04 0.041
0.32 0.0126
10X
3.20 0.126
4.24 0.167
5.28 0.208
8X
0.50 0.0196
SCALE 8:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP5008/D

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